1. Field of the Invention
The present invention relates to a flip-flop having a modified function. More specifically, the present invention relates to a flip-flop having a reset preferential function, particularly suited for implementation by an integrated circuit.
2. Description of the Prior Art
As well known, flip-flops are utilized as one of the most fundamental elements of a logic circuit in implementing various digital processing circuitry. Various types of flip-flops have been proposed depending on applications. Some applications require a flip-flop having a modified function. For example, a phase comparator for comparing the phases of two digital input signals can be implemented by using a pair of flip-flops having a reset preferential function, as to be more fully described subsequently. As well known, a flip-flop typically comprises set and reset input terminals, and set and reset output terminals. As briefly described previously, in a certain application, a flip-flop is desired wherein the flip-flop is set responsive to the edge, such as the leading edge, of a clock signal to be applied to the set input terminal but is forcibly or preferentially reset responsive to the reset signal to be applied to the reset input terminal. In the light of the modified function of such a flip-flop, the flip-flop may be referred to as "a flip-flop having a reset preferential function". A flip-flop having a reset preferential function may be advantageously utilized in implementing a phase comparator for comparing the phases of two digital input signals.
FIG. 1 shows a logical diagram of an example of a flip-flop structured such that the same is set responsive to the leading edge of a clock signal to be applied to the set input terminal of the flip-flop but is preferentially or forcibly reset responsive to a reset signal to be applied to the reset input terminal of the flip-flop. The flip-flop shown in FIG. 1 comprises a first flip-flop unit F1 implemented by cross connected paired NOR gates G1 and G2, a second flip-flop unit F2 implemented by cross connected paired NOR gates G3 and G4, a NOR gate G5 and an inverter IV. The reset inputs of the flip-flop units F1 and F2 comprising one input of the NOR gates G1 and G3 are connected to the reset input terminal RE. The set input of the flip-flop F1 comprising one input of the NOR gate G2 is connected to the output of the NOR gate G5. The NOR gate G5 is connected to receive the reset output comprising the output of the NOR gate G4 of the flip-flop unit F2 and the output of the inverter IV. The set input of the flip-flop unit F2 comprising one input of the NOR gate G4 is connected to receive the output of the inverter IV. The input of the inverter IV is connected to the set input terminal CL adapted to receive a clock signal. The reset output of the flip-flop F2 comprising the output of the NOR gate G4 is also applied to another input of the NOR gate G1 of the flip-flop F1. The set output of the flip-flop unit F1 is connected to a set output terminal and the reset output of the flip-flop F1 is connected to a reset output terminal.
Referring to FIG. 1, the FIG. 1 flip-flop comprises the basic flip-flop unit F1 adapted to be responsive to the clock signal to be applied to the set input terminal of the flip-flop F1 and to be responsive to the reset signal to be applied to the reset input terminal of the flip-flop F1, which basic flip-flop unit F1 is accompanied by the additional flip-flop unit F2, which is set responsive to the inversion of the clock signal applied to the clock input terminal CL and reset responsive to the reset input signal applied to the reset input terminal RE, which reset output obtainable from the NOR gate G4 of the flip-flop unit F2 is applied to the NOR gate G5 to disable the transfer path of the clock signal comprising the inverter IV and the NOR gate G5. As a result, a desired reset preferential function can be achieved. Even if the reset signal once applied to the reset input terminal RE is interrupted, the flip-flop unit F2 keeps a reset state. Therefore, even if in such a situation the clock signal is kept applied, the fact that the clock signal is kept applied is disabled by the NOR gate G5, with the result that only the leading edge of the clock signal is effective to the set input terminal of the first flip-flop unit F1. Thus, a desired function of being responsive to only the leading edge of a clock signal to be applied to the set input terminal can be achieved. As seen from FIG. 1, the FIG. 1 flip-flop comprises five NOR gates and one inverter.
FIG. 2 shows a schematic diagram of the FIG. 1 flip-flop implemented by an integrated circuit comprising insulated gate field effect transistors. Referring to FIG. 2, the corresponding portions have been denoted by the same reference characters. It would be appreciated that the inverter is implemented by an insulated gate field effect transistor serving as a switching transistor which is connected in series with another insulated gate field effect transistor serving as a load resistor and the NOR gates are each implemented by a parallel connection of two or three insulated gate field effect transistors serving as a switching transistor which is connected in series with another insulated gate field effect transistor serving as a load resistor, as well known. As seen from FIGS. 1 and 2, the FIG. 1 flip-flop is implemented by a relatively large number of insulated gate field effect transistors, which degrades the scale of integration in implementing the flip-flop in an integrated circuit and also degrades the speed of operation.
FIG. 3 shows a logical diagram of another example of a flip-flop structured such that the same is set responsive to the leading edge of the clock signal to be applied to the set input terminal and is preferentially reset responsive to the reset signal applied to the reset input terminal. Referring to FIG. 3, the FIG. 3 flip-flop comprises a flip-flop unit F11 comprising a cross connection of paired NOR gates G12 and G13. The reset input terminal RE comprises one input of the NOR gate G13. The set input terminal comprising one input of the NOR gate G12 connected to receive the output of a NOR gate G11 one input of which is connected directly to the output of an inverter I1 and the other input of which is connected through a series connection of inverters I2, I3, and I4 to the output of the inverter I1. The input of the inverter I1 is connected to the clock terminal CL. The output of the NOR gate G13 is connected to the set output Q and through an inverter I5 to the reset output Q. Referring to FIG. 3, since an inversion of the clock is directly applied to one input of the NOR gate G11 and the inversion of the clock is applied through the three inverters I2, I3 and I4 to another input of the NOR gate G11, the NOR gate G11 proves to receive an inverted clock and a non-inverted but delayed clock as delayed through the three inverters I2, I3 and I4. As a result, the NOR gate G11 provides a pulsive output which corresponds to the leading edge of the clock signal. Thus, the flip-flop shown in FIG. 3 is made responsive to the leading edge of the clock to be set. On the other hand, the reset input terminal of the flip-flop unit F11 is directly connected to the reset input terminal RE. The fact that the set input terminal of the flip-flop unit F11 is supplied with a pulsive input representative of the leading edge of the clock signal and the reset input terminal of the flip-flop unit F11 is supplied directly with the reset signal makes the FIG. 3 flip-flop responsive to the leading edge of the clock signal to be set and responsive to the reset signal to be preferentially reset.
As seen from FIG. 3, the FIG. 3 flip-flop has been implemented using a similar large number of logical components. This can be better understood by referring to FIG. 4, which shows a schematic diagram of the FIG. 3 flip-flop. Referring to FIG. 4, the corresponding portions have been denoted by the same reference characters. It would be appreciated that the inverters are each implemented by a series connection of an insulated gate field effect transistor serving as a switching device and another insulated gate field effect transistor serving as a load resistor, and the NOR gates are implemented by a parallel connection of insulated gate field effect transistors serving as a switching device and another insulated gate field effect transistor connected in series with the said parallel connection serving as a load resistor. The flip-flop as shown in FIGS. 3 and 4 again suffers from the disadvantages that the same requires many circuit components such as insulated gate field effect transistors, which degrades the scale of integration in implementing the flip-flop in an integrated circuit and also degrades the speed of operation.
As described previously, a flip-flop structured such that the same is set responsive to the leading edge of the clock signal and is preferentially reset responsive to the reset input signal may be advantageously utilized in implementing a phase comparator for comparing the phases of two digital input signals. Since a digital type phase comparator makes a phase comparison responsive to the edges of digital signals, several advantages result that the duty cycle of the digital input signals does not matter, that much less malfunction occurs by virtue of the harmonics of the input signals, that if a phase lock loop is implemented by the use of such flip-flops the capture range and the lock range of the phase lock loop extend throughout the range where the voltage control oscillator is operable, and so on. For these reasons, of late a digital phase comparator is advantageously utilized in a phase lock loop of a frequency synthesizer implemented in an integrated circuit.
FIG. 5 shows a block diagram of an example of a conventional digital type phase comparator employing flip-flops having a reset preferential function. Such a phase comparator as shown in FIG. 5 is seen in U.S. Pat. No. 3,714,463. Referring to FIG. 5, the phase comparator shown comprises a pair of flip-flops FA and FB having a reset preferential function. The clock input terminal CA of the flip-flop FA is supplied with a reference signal having a reference frequency and phase. The clock input terminal CB of the flip-flop FB is supplied with a signal being compared of the frequency and phase. The reset outputs QA and QB of the flip-flops FA and FB are applied to a NOR gate GE. The output Z of the NOR gate GE is applied to the reset input terminals RA and RB of the flip-flops FA and FB. The output Z of the NOR gate GE is also applied to one input of NOR gates GC and GD. The reset output QA of the flip-flop FA is also applied to another input of the NOR gate GC. The reset output QB of the flip-flop FB is also applied to another input of the NOR gate GD. The output X of the NOR gate GC and the output Y of the NOR gate GD are withdrawn as the outputs representing the phase difference between the reference signal and the signal being compared. As described previously, the flip-flops FA and FB are set responsive to the leading edge of the clock signals applied as a reference signal and a signal being compared to the input terminals CA and CB, whereby the set outputs QA and QB of the flip-flops FA and FB become the high level and the reset outputs QA and QB become the low level, and the flip-flops FA and FB are preferentially reset responsive to the reset signal applied to the reset input terminal RA and RB, whereupon the set output QA and QB become the low level and the reset outputs QA and QB become the high level, which reset state is kept until the following leading edge of the clock signal.
The opertion of the FIG. 5 phase comparator can be better understood with reference to FIG. 6 which shows wave forms of the signals at various portions in the FIG. 5 diagram, wherein each wave form has been identified by the same reference character as used in the FIG. 5 diagram. Referring to FIG. 6, first let it be assumed that in the time period TA the reference signal CA and the signal being compared CB are both in the low level, the flip-flops FA and FB both have been reset, whereby the reset outputs QA and QB are in the high level, and thus the outputs X, Y and Z of the NOR gates GC, GD and GE are in the low level. If and when the reference signal CA turns from the low level to the high level in such a situation, the flip-flop FA is set and the reset output QA turns from the high level to the low level. As a result, the output X of the NOR gate GC turns from the low level to the high level. The time period of such a state has been identified as a time period TB. At the end of the time period TB, the reference signal CA turns from the high level to the low level. However, no change occurs in the storing state. The time period in such a state has been identified as a time period TC. If and when the signal being compared CB turns from the low level to the high level at the beginning of the following time period TD, the flip-flop FB is set and accordingly the reset output QB of the flip-flop FB turns from the high level to the low level. At the same time, the output Y of the NOR gate GD is about to turn from the low level to the high level. At the same time, however, the output Z of the NOR gate GE is also about to turn from the low level to the high level. Therefore, the output Y of the NOR gate GD is immediately brought to the low level. Thus, the NOR gate GD is caused to provide a pulsive output corresponding to one transition. Since the output Z of the NOR gate GE has become the high level, the flip-flops FA and FB both are reset, whereby the reset outputs QA and QB of the flip-flops FA and FB turn from the low level to the high level. As a result, the output X of the NOR gate GC turns from the high level to the low level. Since the flip-flops FA and FB have been reset and the reset outputs QA and QB have become the high level, the output Z of the NOR gate GE turns from the high level to the low level. At the beginning of the following time period identified as TE, the signal being compared CB turns from the high level to the low level. However, no change occurs in the storing state. Referring to FIG. 6, it would be appreciated that two clock signals CA and CB were applied to the terminal CA and CB of the FIG. 5 circuit, wherein the clock signal CA has been advanced by a given phase difference with respect to the clock signal CB, and an output pulse X representative of the phase difference between the leading edges of the clock signals CA and CB was provided. It would be further appreciated that in view of a symmetrical circuit configuration of the FIG. 5 phase comparator, if the clock signal CB had been advanced by a given phase difference with respect to the clock signal CA, then an output pulse Y representing the phase difference between the leading edges of the clock signals CA and CB would have been obtained from the NOR gate GD.
FIG. 7 shows a schematic diagram of the FIG. 5 phase comparator, wherein the flip-flop FA and FB have been implemented by another circuit configuration having a reset preferential function. In the FIG. 7 diagram, the corresponding portions have been denoted by the same reference characters. A terminal DT is a data input and terminals DA and DB are the data input terminals of the flip-flops FA and FB. If and when the FIG. 7 diagram is implemented in an integrated circuit using insulated gate field effect transistors, transistors as many as 45 are required. Such a large number of insulated gate field effect transistors are not preferred in implementing a phase comparator in an integrated circuit form.
The example as shown in FIGS. 5 and 7 can be simplified to some extent by simply omitting the NOR gates GC and GD in the FIGS. 5 and 7 diagram and by directly withdrawing the reset outputs QA and QB of the flip-flops FA and FB as the phase difference outputs X and Y. In such a modified example, however, it has been found that a pulsive output Y as shown in FIG. 6 in case where the clock signal CA is advanced as compared with the clock signal CB becomes larger in the pulse width, which makes it difficult to descriminate the phase difference output from an undesired pulsive output and thus degrades the sensitivity of the phase comparator. Nevertheless, merely a few number of circuit components can only be reduced. Thus, such a modified example still suffers from the advantages that a relatively large number of insulated gate field effect transistors are required in implementing a desired phase comparator in an integrated circuit and the speed of operation is not sufficiently high.
Another example of a digital type phase comparator of interest is seen in the U.S. Pat. No. 3,610,954. FIG. 8 shows a logical diagram of such a digital type phase comparator of interest disclosed in the above referenced U.S. Pat. No. 3,610,954. Referring to FIG. 8, the terminal REF is supplied with a reference signal, a terminal SIG is supplied with a signal being compared, and the terminals X and Y are those for withdrawing the phase difference outputs. The operation of the FIG. 8 phase comparator is similar to that of the FIG. 5 phase comparator but can be fully understood when the above referenced U.S. Patent is referred to. FIG. 9 shows a schematic diagram of the FIG. 8 example implemented in an integrated circuit using insulated gate field effect transistors, wherein the corresponding portions have been denoted by the same reference characters. As readily understood from the FIG. 9 illustration, since the circuit configuration of the FIGS. 8 and 9 example is rather complicated, a broader area is required for implementation in an integrated circuit, which increases a stray capacitance and causes a delay of signals and thus lowers the sensitivity of a phase comparator.